This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to improve the properties of bottom electrode structures in semiconductor devices.
In semiconductor circuits, the devices fabricated in or on a semiconductor substrate are connected with a metallic interconnection structure made of metal lines and “vias” which interconnect the metal lines. The metal lines are arranged in horizontal layers, i.e. parallel to the substrate, and separated by layers of dielectrics while vias are disposed vertically in openings in the dielectric to interconnect the layers of metal lines.
Magnetoresistive random-access memory (MRAM) is a non-volatile random-access memory technology. Although the technology has been in development since the mid-1980s, the improvements in existing memory technologies, e.g., in flash RAM and DRAM, have kept MRAM in a niche role. Nonetheless, the technology has great promise such that many believe that MRAM will eventually become the dominant type of memory in the market. Data in MRAM is not stored as electric charge or current flows, but by magnetic storage elements. The elements are formed from ferromagnetic plates typically comprised of a magnetic tunnel junction (MTJ) material. Each of the plates hold a magnetization, separated by a thin insulating layer. In some MRAMs, one of the two plates is a permanent magnet set to a particular polarity, while the other plate magnetization is variable, so that it can be changed to match that of an external electromagnetic field to store memory.
As the dimensions of the interconnection structure for an MRAM device have become smaller, challenges have been experienced to provide an adequate contact structure. One of the problems is that there is a chemical reaction between the pedestal and microstud elements of the contact structure resulting in galvanic related corrosion. Another of the problems experienced is that the fill quality of the current process is inadequate, leading to device reliability problems. Another issue is that redeposition of the already deposited layers causes reliability problems in the device structure, and therefore, the integrated circuit in which it is incorporated.
Thus, producing an improved interconnection structure is desirable. The present disclosure presents a method and structure to address the above described problems.